| 摘要 |
A phase control circuit includes a first duty cycle correction circuit configured to correct a duty cycle of a clock signal; a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit; and a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop, wherein the first duty cycle correction circuit and the second duty cycle correction circuit are selectively activated depending upon an operating condition. |
