Variably delayed wakeup transition

摘要

A computing system includes a controller to undergo a variably delayed wakeup transition. The controller is to transition a processing module from an idle state to an active state in response to successive assertions of a wakeup interrupt command. The system includes a variable delay module to vary delay lengths between assertion and execution of each of the successive wakeup interrupt commands during the wakeup transition to substantially cause power supply components to vibrate in a non-periodic manner.