| 摘要 |
PROBLEM TO BE SOLVED: To enhance processing performance of an arithmetic processing device by responding to a request source with an appropriate state in response to a load request to a low-order cache memory.SOLUTION: The arithmetic processing device includes an L1 cache memory storing data, a plurality of CPU cores outputting requests while performing arithmetic processing, a L2 cache memory connected to the plurality of CPU cores, the L2 cache memory responds to the CPU core which sent a request in the case where a request requests target data stored in none of the L1 cache memories provided in the plurality of CPU cores and is a load request that allows the target data stored in other CPU cores with non-exclusive information indicating the target data is the non-exclusive data and the target data, and responds to the CPU core which sent a request in the case where the request is the load request that does not allow storing the target data in other CPU cores with exclusive information indicating the target data is the exclusive data and the target data. |
