| 摘要 |
A pipelined A/D converter, for which a plurality of stages 1 to N, containing a multiplying digital to analog converter (MDAC), are cascaded, is configured so a Gain-AMP (12) contained in the MDAC at a SPM comprises: MOS transistors (Mx1 and Mx2) as a differential pair joining an output terminal to a next stage sampling capacitor (CsI+1); MOS transistors (My1 and My2) as a load section connected to the differential pair; a current source (I3) for supplying a current to the MOS transistors (Mx1 and Mx2) serving as the differential pair; and current sources (I1 and I2) for regulating a current flowing to the MOS transistors (My1 and My2) serving as the load section. |
