发明名称 DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER WITH ERROR SUPPRESSION
摘要 A delta-sigma analog-to-digital converter (DeltaSigma ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.
申请公布号 US2014070969(A1) 申请公布日期 2014.03.13
申请号 US201314016246 申请日期 2013.09.03
申请人 MEDIATEK INC. 发明人 SHU YUN-SHIANG
分类号 H03M3/00 主分类号 H03M3/00
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