| 摘要 |
PROBLEM TO BE SOLVED: To allow for video signal processing of different horizontal synchronizing frequencies with a simple configuration.SOLUTION: A digital video processor includes an FIFO memory 11, an FIFO control circuit 12 for generating and outputting a write clock of the FIFO memory 11, and a video processing circuit 13 performing video processing of an output signal from the FIFO memory 11. The FIFO control circuit 12 creates a write clock of about 1/2 of a system clock when the horizontal synchronizing frequency of a video input signal is 1 time, and allows the write clock to be outputted to the FIFO memory 11. When the horizontal synchronizing frequency of a video input signal is 2 times, the FIFO control circuit 12 creates a write clock of about 1 time of a system clock, and allows the write clock to be outputted to the FIFO memory 11. Consequently, a video signal having a horizontal synchronizing frequency, different about 2 times, can be processed. |
