| 摘要 |
<p>A data processing system 2 includes an interrupt controller having a priority level arbitrator 10 and trigger circuitry 12. The priority level arbitrator 10 and the trigger circuitry 12 operate in parallel to process interrupt signals received by an interrupt signal receiver 6. The trigger circuitry 12 generates a trigger signal initiating interrupt processing before the priority level arbitrator 10 has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.</p> |
