| 摘要 |
A memory device comprises: a plurality of memory blocks refreshed in response to a refresh signal corresponding to each of the memory blocks; a command decoder configured to generate an internal refresh command by decoding an external input command; a refresh control unit configured to activate the refresh signals corresponding to a first number of memory blocks at one time whenever the internal refresh command is activated upon setting up a first mode, and activate refresh signals corresponding to a second number -the second number is smaller than the first number- of memory blocks at one time whenever the internal refresh command is activated upon setting up a second mode; and an address counter configured to change a value of a low address transmitted to the memory blocks whenever one of the predetermined refresh signals is activated. [Reference numerals] (410) Command input unit; (420) Address input unit; (430) Command decoder; (440) Setting circuit; (450) Refresh control unit; (460) Address counter |
