Shift register and one-of-many shift register

摘要

A shift register has a first latch and a second latch and a first output circuit and a second output circuit. The first latch and the second latch are series-connected. The latches are implemented to take over a signal state applied to their data inputs in a transparent state and to maintain the taken-over signal state in a non-transparent operating state. Clock inputs of the latches are switched such that the second latch is in the transparent operating state when the first latch is in the non-transparent operating state and vice versa. The first output circuit is implemented to provide a predetermined level independent of the signal state existing in the first latch at a first shift register output of the shift register in the transparent operating state and to provide a level depending on the signal state stored in the first latch in the non-transparent operating state of the first latch. The second output circuit is implemented to provide a predetermined level independent of the signal state existing in the second latch at a second shift register output of the shift register in the transparent operating state of the second latch and to provide a level depending on the signal state stored in the second latch in the non-transparent operating state of the second latch.