| 摘要 |
A memory device comprises: a plurality of memory blocks; a setting circuit for setting a first mode of refreshing a first number of memory blocks at one time, and a second mode of refreshing a second number of memory blocks -the second number is less than the first number-; a storage circuit for storing additional refresh information; and a refresh control unit for controlling that a second number of memory blocks are refreshed at one time whenever a refresh command is applied if the additional refresh information is inactivated, and controlling that a first number of memory blocks are refreshed at one time whenever the refresh command is applied if the additional refresh information is activated, when the second mode is set by the setting circuit. [Reference numerals] (410) Command input unit; (420) Address input unit; (430) Command decoder; (440) Setting circuit; (450) Storage circuit; (460) Refresh control unit; (470_BG0,470_BG1,470_BG2,470_BG3) Address counter unit |
