发明名称 WAFER LEVEL CHIP SCALE PACKAGE
摘要 The present disclosure provides a semiconductor device including a semiconductor element having a first surface and a second surface, which is opposite to the first surface, and a conductive via disposed on the semiconductor element. The semiconductor element includes a die; a first redistribution layer positioned on the first surface, wherein the first redistribution layer is configured to fan out the die; and a second redistribution layer positioned on the second surface of the semiconductor element. The conductive via is configured to electrically connect the first redistribution layer and the second redistribution layer, wherein the sizes of the two ends of the conductive via are different and the die can be electrically coupled to another semiconductor device through the conductive via.
申请公布号 US2014061880(A1) 申请公布日期 2014.03.06
申请号 US201313935911 申请日期 2013.07.05
申请人 CHIPMOS TECHNOLOGIES INC. 发明人 LIAO TSUNG JEN
分类号 H01L21/768;H01L23/538 主分类号 H01L21/768
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