发明名称 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING UNIT, AND CONTROL METHOD OF ARITHMETIC PROCESSING UNIT
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic system which efficiently achieves processing of obtaining a correction value for a value resulting from addition/subtraction of fixed-precision floating-point numbers.SOLUTION: The arithmetic circuit includes: an arithmetic unit which generates, as a shift amount, a value obtained by subtracting a second exponent and a preceding zero count value of a first mantissa from a first exponent and generates a third exponent obtained by subtracting a preceding zero count value of the first mantissa and a first prescribed value from the first exponent; a shift unit which generates a shifted mantissa obtained by shifting the first mantissa on the basis of the shift amount; an addition unit which generates an addition value obtained by adding the shifted mantissa and a part of a second mantissa and generates a carry due to the addition; a prediction unit which receives the shifted mantissa and the carry to generate flags showing the occurrence of digit overflow and digit cancellation respectively; and a generation unit which generates a correction value mantissa and a correction value exponent on the basis of the addition value, the third exponent, and the flags.
申请公布号 JP2014041563(A) 申请公布日期 2014.03.06
申请号 JP20120184594 申请日期 2012.08.23
申请人 FUJITSU LTD 发明人 SHINOMIYA KENSUKE;KITAMURA KENICHI
分类号 G06F7/483 主分类号 G06F7/483
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