发明名称 WIDE-RANGE GLITCH-FREE ASYNCHRONOUS CLOCK SWITCH
摘要 Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.
申请公布号 US2014062548(A1) 申请公布日期 2014.03.06
申请号 US201213604795 申请日期 2012.09.06
申请人 HWANG CHANGKU;TURULLOLS SEBASTIAN;JIAN DAISY;VAHIDSAFA ALI 发明人 HWANG CHANGKU;TURULLOLS SEBASTIAN;JIAN DAISY;VAHIDSAFA ALI
分类号 H03L7/00;H03L7/06 主分类号 H03L7/00
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