| 摘要 |
A timing analysis device includes a storage unit and a processing unit. The processing unit performs storage processing and analysis processing. The storage processing stores circuit information of a circuit to be analyzed, timing constraint information defining timing constraints on the circuit, delay information defining a plurality of delay values associated with a plurality of cells constituting the circuit, and delay upper limit information including at least one delay upper limit for setting an upper limit to the plurality of delay values associated with the plurality of cells into a storage unit. The analysis processing generates a timing analysis result of a circuit to be analyzed, with delay value change processing that changes at least one of the plurality of delay values to the delay upper limit, using the changed delay upper limit in addition to the circuit information, the timing constraint information and the delay information. |
