发明名称 Mismatch Error Reduction Method and System for STT MRAM
摘要 The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
申请公布号 US2014063923(A1) 申请公布日期 2014.03.06
申请号 US201213605693 申请日期 2012.09.06
申请人 JEFREMOW MIHAIL;ALLERS WOLF;OTTERSTEDT JAN;PETERS CHRISTIAN;KERN THOMAS;INFINEON TECHNOLOGIES AG 发明人 JEFREMOW MIHAIL;ALLERS WOLF;OTTERSTEDT JAN;PETERS CHRISTIAN;KERN THOMAS
分类号 G11C7/06;G11C11/16 主分类号 G11C7/06
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