| 摘要 |
Memory address generation for digital signal processing, such as convolutional delinterleaving operations, is described. A digital signal processing system-on-chip (100) utilises an on-chip memory space (102), e.g. static RAM (SRAM) that is shared between functional blocks of the system. An on-chip direct memory access (DMA) controller 106 comprises an address generator 210 that generates sequences of read 212 and write 214 memory addresses for data items being transferred between the on-chip memory (102) and a paged memory device (112) via port 204, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses, in accordance with different read modes and write modes. This enables interleaving or deinterleaving operations to be performed by DMA controller 106 as part of a data transfer between internal or paged memory with a dedicated memory for interleaving operations is not being required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM. |
