| 摘要 |
<p>A data input circuit comprises: a driving clock signal generating unit which delays a final clock generated in response to pulses of a sampling clock by shifting, and generates a driving clock signal from the delayed final clock; a data transfer unit which outputs an input data to a write input data in response to the driving clock signal; and a write driver which drives a global line by receiving the write input data in response to the driving clock signal. [Reference numerals] (10) Data buffer; (11) DQS buffer; (12) Command decoder; (13) Clock buffer; (2) Data array unit; (31) Clock sampling unit; (33) Final clock generation unit; (35) Life latch signal generator; (4) Data latch unit; (7) Driving clock signal generation unit; (8) Data transmitting unit; (9) Light driver</p> |
