发明名称 |
Circuit for generating an output clock signal synchronized to an input clock signal |
摘要 |
A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal. |
申请公布号 |
US8665928(B1) |
申请公布日期 |
2014.03.04 |
申请号 |
US201113030558 |
申请日期 |
2011.02.18 |
申请人 |
KLEIN MATTHEW H.;TAYLOR DAVID F.;XILINX, INC. |
发明人 |
KLEIN MATTHEW H.;TAYLOR DAVID F. |
分类号 |
H04B3/36;H03D3/24;H04L25/20;H04L25/52 |
主分类号 |
H04B3/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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