发明名称 System, method, and computer program product for optimizing pins
摘要 The present disclosure relates to a computer-implemented method for synthesis of device I/O associated with a printed circuit board (PCB) design. The method may include generating a first programmable device model and a second device model. The method may further include determining one or more pin assignments associated with the first programmable device model and the second device model based upon, at least in part, one or more of a breakout pattern, a breakout location and a fanout location, the one or more pin assignments configured to minimize one or more crossovers.
申请公布号 US8667454(B1) 申请公布日期 2014.03.04
申请号 US201113160992 申请日期 2011.06.15
申请人 SUBRAHMANYA NARASIMHA MURTHY PALLA;VEDULA SRINIVASA RAVI;PATEL NISHITKUMAR MANHARBHAI;GUPTA NAGESH C.;CADENCE DESIGN SYSTEMS, INC. 发明人 SUBRAHMANYA NARASIMHA MURTHY PALLA;VEDULA SRINIVASA RAVI;PATEL NISHITKUMAR MANHARBHAI;GUPTA NAGESH C.
分类号 G06F17/50 主分类号 G06F17/50
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