发明名称 |
Memory device controller |
摘要 |
A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register. |
申请公布号 |
US8667232(B2) |
申请公布日期 |
2014.03.04 |
申请号 |
US20100651827 |
申请日期 |
2010.01.04 |
申请人 |
DE SANTIS LUCA;CONENNA PASQUALE;MICRON TECHNOLOGY, INC. |
发明人 |
DE SANTIS LUCA;CONENNA PASQUALE |
分类号 |
G06F12/00;G06F13/00;G06F13/16;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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