发明名称 |
Filtering circuit, phase identity determination circuit and delay locked loop |
摘要 |
A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock. |
申请公布号 |
US8664987(B2) |
申请公布日期 |
2014.03.04 |
申请号 |
US201213607234 |
申请日期 |
2012.09.07 |
申请人 |
KWON DAE-HAN;KIM YONG-JU;SONG TAEK-SANG;SK HYNIX INC. |
发明人 |
KWON DAE-HAN;KIM YONG-JU;SONG TAEK-SANG |
分类号 |
H03K5/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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