| 摘要 |
The ratio of the output frequency of the PLL to the reference frequency is governed by the ratio of the feedback divider to the output divider. For the case of a fixed-point delta-sigma modulator based PLL, the feedback divide factor can only be a non-recurring/terminating rational number in base-2 (binary) system and the output divide ratio is constrained to be an integer. Hence, the range or resolution of the output frequencies that are possible is inherently limited. To solve this problem, an additional gain factor is introduced in the feedback loop. The gain factor is determined by finding an initial gain factor for which the value of the feedback divide ratio can be represented precisely in the binary format. The closest power of two larger than the initial gain factor is used as the denominator to divide the initial gain factor. The present system and method increases the resolution of such a PLL, while actually saving area/power, by introducing an additional factor within the modulator and also by not affecting the analog part of the circuit. |
