发明名称 High Precision Timer in CPU Cluster
摘要 A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.
申请公布号 US2014056319(A1) 申请公布日期 2014.02.27
申请号 US201313799167 申请日期 2013.03.13
申请人 EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC. 发明人 HELLWIG MATHIAS
分类号 H04L7/00 主分类号 H04L7/00
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