| 摘要 |
<p>The power semiconductor device of the embodiment includes a substrate, a buffer layer arranged on the substrate, a barrier layer arranged on the buffer layer, a gate insulating layer arrange don the barrier layer, a gate electrode arranged on the upper part of the gate insulating layer, a source and drain contact penetrating the insulting layer to touch the barrier layer and separated between the gate electrodes, and at least one electric field dispersion layer arranged between the gate electrode and the drain contact and penetrating the gate insulating layer to touch the barrier layer. [Reference numerals] (AA) Second direction; (BB) First direction</p> |
