| 摘要 |
A semiconductor memory apparatus comprises a normal CAS latency setting unit, a test CAS latency setting unit, a selection unit, an output enable signal generation unit, and an output driver. The normal CAS latency setting unit sets a normal CAS latency value based on mode register set address information. The test CAS latency setting unit increases (or decreases) an initially-set test CAS latency value in response to control signal pulses which are sequentially applied, during a test mode. The selection unit selectively transmits the normal CAS latency value or the test CAS latency value depending on whether a current mode is in the test mode. The output enable signal generation unit receives the normal CAS latency value or the test CAS latency value transmitted from the selection unit, and generates an output enable signal by shifting a read signal pulse applied from the outside according to the CAS latency value. The output driver outputs read data to the outside at a time when the output enable signal is activated. [Reference numerals] (10) Normal CAS latency setting unit; (20) Test CAS latency setting unit; (30) Selection unit; (40) Output enable signal generation unit; (50) Output driver |
