发明名称 |
MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD |
摘要 |
PROBLEM TO BE SOLVED: To improve execution performance of a CPU.SOLUTION: Other CPU detects coincidence between an instruction address for a task B held in a table to access a shared memory and a program counter for the other CPU, as preprocessing of access. The other CPU determines whether a value of an access flag is a minus by checking the access flag. If a value of the access flag is 0, the other CPU determines that one CPU is accessing the shared memory and the other CPU switches a task from the task B to a task C in a ready queue 121. |
申请公布号 |
JP2014038656(A) |
申请公布日期 |
2014.02.27 |
申请号 |
JP20130221663 |
申请日期 |
2013.10.24 |
申请人 |
FUJITSU LTD |
发明人 |
KURIHARA YASUSHI;YAMASHITA KOICHIRO;YAMAUCHI HIROMASA;SUZUKI TAKAHISA |
分类号 |
G06F9/50 |
主分类号 |
G06F9/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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