发明名称 TICC-PARADIGM TO BUILD FORMALLY VERIFIED PARALLEL SOFTWARE FOR MULTI-CORE CHIPS
摘要 This invention teaches a way of implementing formally verified massively parallel programs, which run efficiently in distributed and shared-memory multi-core chips. It allows programs to be developed from an initial abstract statement of interactions among parallel software components, called cells, and progressively refine them to their final implementation. At each stage of refinement a formal description of patterns of events in computations is derived automatically from implementations. This formal description is used for two purposes: One is to prove correctness, timings, progress, mutual exclusion, and freedom from deadlocks/livelocks, etc. The second is to automatically incorporate into each application a Self-Monitoring System (SMS) that constantly monitors the application in parallel, with no interference with its timings, to identify and report errors in performance, pending errors, and patterns of critical behavior. This invention also teaches a way of organizing shared-memory for multi-processors that minimizes memory interference, protects data and increases execution efficiency.
申请公布号 EP2350825(A4) 申请公布日期 2014.02.26
申请号 EP20090820927 申请日期 2009.05.14
申请人 SRINIVASAN, CHITOOR, V. 发明人 SRINIVASAN, CHITOOR, V.
分类号 G06F9/46;G06F9/44 主分类号 G06F9/46
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