发明名称 |
Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration |
摘要 |
An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips. |
申请公布号 |
US8658533(B2) |
申请公布日期 |
2014.02.25 |
申请号 |
US201113044660 |
申请日期 |
2011.03.10 |
申请人 |
EDELSTEIN DANIEL C;NOGAMI TAKESHI;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
EDELSTEIN DANIEL C;NOGAMI TAKESHI |
分类号 |
H01L23/48;H01L21/44;H01L23/52;H01L29/40 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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