发明名称 Switch level circuit with dead time self-adapting control
摘要 A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time. The control module comprises a sampling circuit (16) for detecting the current dead time at the node (LX), an adjusting circuit (17) for buffering and converting the sampling voltage sampled by the sampling circuit (16), and a controlled delay unit (15) equipped with an external control input terminal, wherein the controlled delay unit (15) delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor (11) as a control signal. The switch level circuit (110) has simple structure, better performance and wide application range.
申请公布号 US8659345(B2) 申请公布日期 2014.02.25
申请号 US201013515801 申请日期 2010.10.26
申请人 XU SHEN;SUN WEIFENG;YANG MIAO;LIU SICHAO;JIN YOUSHAN;LU SHENGLI;SHI LONGXING;SOUTHEAST UNIVERSITY 发明人 XU SHEN;SUN WEIFENG;YANG MIAO;LIU SICHAO;JIN YOUSHAN;LU SHENGLI;SHI LONGXING
分类号 H03K17/687 主分类号 H03K17/687
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