| 摘要 |
<p>Disclosed is a memory sharing circuit for sharing a memory, the circuit including a plurality of unit processors connected to the memory, wherein the unit processor includes a buffer configured to be connected through the memory, a buffering address and a data bus, and a processor configured to be connected to the buffer for access to the memory through the buffer, and wherein the plurality of unit processors is configured to allow the processors to share the memory by preventing address/data bus collision for access to the memory by the processors.</p> |
