发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To inhibit capacity decline of a capacitor caused by parasitic capacitance of a semiconductor element.SOLUTION: In a voltage lower control circuit 10 which forms a DC-DC converter 16 provided in an IC 12, an end of a capacitor 36 for bootstrap is connected to an LX node 26A and the other end of the capacitor 36 is connected to a node 38B having higher potential than the LX node. In a transistor Ma, an N well 44 formed on a Psub is connected to the node 38B, and a P well 46 formed in the N well and a source S formed in the P well are connected to the LX node. With this configuration, parasitic capacitance between the N well and the P well of the transistor functions as electrostatic capacitance for bootstrap thereby to inhibit capacity decline of the electrostatic capacitance for bootstrap.
申请公布号 JP2014036489(A) 申请公布日期 2014.02.24
申请号 JP20120175884 申请日期 2012.08.08
申请人 FUJITSU LTD 发明人 SAKAI YASUBUMI
分类号 H02M3/145 主分类号 H02M3/145
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