| 摘要 |
A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge. |
