发明名称 |
Programmable Logic Unit and Method for Translating and Processing Instructions Using Interpretation Registers |
摘要 |
An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions). |
申请公布号 |
US2014052964(A1) |
申请公布日期 |
2014.02.20 |
申请号 |
US201314064157 |
申请日期 |
2013.10.27 |
申请人 |
3DIABS INC., LTD.;3DLABS INC., LTD. |
发明人 |
BLOOMFIELD JONATHAN;ROBSON JOHN;MURPHY NICK |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|