| 摘要 |
PROBLEM TO BE SOLVED: To provide a power supply wiring structure for reducing a chip area.SOLUTION: Each of a first power supply wiring network and a second power supply wiring network respectively supplying a first power source and a second power source comprises: a first wiring formed into a ring shape on a first wiring layer; plural second wirings formed on a second wiring layer positioned between the first wiring layer and a silicon substrate and in parallel to a first direction; and plural third wirings formed on a third wiring layer positioned between the second wiring layer and the silicon substrate and in parallel to a second direction orthogonal to the first direction. In each power supply wiring network, first vias are formed on the plural second wirings and the third wirings at one or more crossing parts, so as to constitute a lattice-like electrically connected power supply wiring. The lattice-like power supply wiring is electrically connected to the first wiring. When seen in a third direction in which the first wiring is perspectively seen from the silicon substrate, the first wiring is formed at an upper part of a region of the lattice-like power supply wiring. |
