发明名称 Layout Circuit Optimization For Deep Submicron Technologies
摘要 An integrated circuit is disclosed that has substantially continuous active diffusion regions within its diffusion layers. Active regions of semiconductor devices can be fabricated using portions of these substantially continuous active diffusion regions. Stress can be applied to these semiconductor devices during their fabrication which leads to substantially uniform stress patterns throughout the integrated circuit. The substantially uniform stress patterns can significantly improve performance of the integrated circuit.
申请公布号 US2014048889(A1) 申请公布日期 2014.02.20
申请号 US201213628839 申请日期 2012.09.27
申请人 BROADCOM CORPORATION 发明人 BITTERLICH STEFAN JOHANNES
分类号 H01L27/092 主分类号 H01L27/092
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