发明名称 CACHE MEMORY CONTROLLER AND CACHE MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To reduce data transfer processing between a main memory and a cache memory in the case where there is processing using data which does not need data holding after a read request from an access master.SOLUTION: A cache memory controller includes transfer attribute management means 50 for defining the necessity of data holding after reading from an access master in each memory area obtained by dividing a memory area of a main memory, hit detection means 10 for detecting whether to be a cache error to an access request, and request control means 30 for securing a cache line in a cache memory in the case of detecting a cache error when receiving a write request from the access master, and writing data subjected the write request from the access master in the secured cache line without performing data transfer from the main memory to the cache memory if data holding after reading a memory area including an address to which the access master performs the write request is defined as unnecessary.
申请公布号 JP2014032555(A) 申请公布日期 2014.02.20
申请号 JP20120173206 申请日期 2012.08.03
申请人 MITSUBISHI ELECTRIC CORP 发明人 KISHIMA JUNKO
分类号 G06F12/08 主分类号 G06F12/08
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