发明名称
摘要 Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 to 103) and an inverter (501)); and a circuit for obtaining a large hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 and 104) and the inverter (501)).
申请公布号 JP5421075(B2) 申请公布日期 2014.02.19
申请号 JP20090258413 申请日期 2009.11.11
申请人 发明人
分类号 H03K19/0175;H03K17/30;H03K17/687 主分类号 H03K19/0175
代理机构 代理人
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