发明名称 |
Sensing FET integrated with a high-voltage transistor |
摘要 |
In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. |
申请公布号 |
US8653583(B2) |
申请公布日期 |
2014.02.18 |
申请号 |
US20070707586 |
申请日期 |
2007.02.16 |
申请人 |
PARTHASARATHY VIJAY;BANERJEE SUJIT;MANLEY MARTIN H.;POWER INTEGRATIONS, INC. |
发明人 |
PARTHASARATHY VIJAY;BANERJEE SUJIT;MANLEY MARTIN H. |
分类号 |
H01L29/76 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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