发明名称 |
Low voltage write time enhanced SRAM cell and circuit extensions |
摘要 |
A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode. |
申请公布号 |
US8654570(B2) |
申请公布日期 |
2014.02.18 |
申请号 |
US201113339587 |
申请日期 |
2011.12.29 |
申请人 |
GROVER ANUJ;VISWESWARAN GANGAIKONDAN SUBRAMANI;STMICROELECTRONICS INTERNATIONAL N.V. |
发明人 |
GROVER ANUJ;VISWESWARAN GANGAIKONDAN SUBRAMANI |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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