TIMING GENERATION AND FORMAT APPARATUS IN LARGE SCALE INTEGRATED CIRCUIT TESTER

摘要

Disclosed is a timing generation and format apparatus in a large scale integrated circuit tester which can realize timing required for each pin by using a rate and timing generate (Rate & timing generator) in a field programmable gate array (FPGA) in case of realizing a pattern generator (PG) using the FPGA. The disclosed timing generation and format apparatus in a large scale integrated circuit tester comprises: a communication interface part for interfacing data with a host terminal outputting a command and pattern data to test a large scale integrated circuit (LSI); and a pattern generator which is linked with the communication interface part, and tests the LSI by generating a test pattern according to a test command transmitted from the host terminal, and processes a waveform of output data by generating plural different timings through a timing and format unit comprised in the inside. [Reference numerals] (110) Host terminal; (120) Network; (130) Communication interface part; (160) Pattern generator