| 摘要 |
The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. In a case where a predetermined LDPC code having a code length of 16200 bits and a code rate of 8/15 is mapped on 256 signal points, and the (#i+1)th bit counted from the uppermost bit among 8×1 sign bits and the (#i+1)th bit counted from the uppermost bit among 8×1 symbol bits of one symbol are expressed as a bit b#i and a bit y#i, respectively, a demultiplexer performs shuffling to assign a bit b0 to a bit y2, a bit b1 to a bit y6, a bit b2 to a bit y1, a bit b3 to a bit y0, a bit y4 to a bit y7, a bit b5 to a bit y5, a bit b6 to a bit y3, and a bit b7 to a bit y4. The present technique can be applied to transmission systems that transmit LDPC codes, for example. |
