发明名称 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
摘要 Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
申请公布号 US2014047404(A1) 申请公布日期 2014.02.13
申请号 US201314053322 申请日期 2013.10.14
申请人 MENTOR GRAPHICS CORPORATION 发明人 LIN XIJIANG;TSAI KUN-HAN;KASSAB MARK;WANG CHEN;RAJSKI JANUSZ
分类号 G06F17/50 主分类号 G06F17/50
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