| 摘要 |
<p>A semiconductor element according to the embodiment of the present invention includes: an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n- type epi layer which are placed on the first surface of the n+ type silicon carbide substrate; a p type epi layer and an n+ region which are placed in order on the n- type epi layer; a trench which penetrates the n+ region and the p type epi layer and is placed on the n- type epi layer; a gate insulation film which is placed in the trench; a gate electrode which is placed on the gate insulation film; an oxide film which is placed on the gate electrode; a source electrode which is placed on the p type epi layer, the n+ region, and the oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The n type pillar regions and the p type pillar regions are placed inside the n- type epi layer, are apart from the trench, and are not placed on the area corresponding to the lower part of the trench.</p> |
