Inverter circuit comprising density of states engineered field effect transistors

摘要

An essentially planar inverter circuit comprises an n-channel transistor employing a first layer structure and a p-channel transistor employing a second layer structure. The first layer structure comprises a first semiconductor layer having a conduction band minimum E C1 ; a second semiconductor layer having a first discrete hole level H 0 ; a first wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a first gate dielectric layer (604) disposed above the first semiconductor layer; and a first gate metal layer (602) disposed above the first gate dielectric layer; wherein the first discrete hole level H 0 is positioned below the conduction band minimum E c1 for zero bias applied to the first gate metal layer. The second layer structure comprises a third semiconductor layer having a second discrete hole level H 0 ; a fourth semiconductor layer having a conduction band minimum E C2 ; a second wide bandgap semiconductor barrier layer disposed between the third and the fourth semiconductor layers; a second gate dielectric layer (904) disposed above the third semiconductor layer; and a second gate metal layer (902) disposed above the second gate dielectric layer; wherein the second discrete hole level H 0 is positioned below the conduction band minimum E c2 for zero bias applied to the second gate metal layer.