发明名称 |
Reducing x-pessimism in gate-level simulation and verification |
摘要 |
Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification. |
申请公布号 |
US8650513(B2) |
申请公布日期 |
2014.02.11 |
申请号 |
US201113174531 |
申请日期 |
2011.06.30 |
申请人 |
SALZ ARTURO;MATURANA GUILLERMO R.;MOON IN-HO;MCILWAIN LISA R.;SYNOPSYS, INC. |
发明人 |
SALZ ARTURO;MATURANA GUILLERMO R.;MOON IN-HO;MCILWAIN LISA R. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
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