发明名称 |
POWER SAVINGS APPARATUS AND METHOD FOR MEMORY DEVICE USING DELAY LOCKED LOOP |
摘要 |
<p>Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.</p> |
申请公布号 |
WO2014022474(A1) |
申请公布日期 |
2014.02.06 |
申请号 |
WO2013US52852 |
申请日期 |
2013.07.31 |
申请人 |
SPANSION LLC |
发明人 |
HASAN, QAMRUL;ZITLAW, CLIFFORD;ROSNER, STEPHAN;DUBOIS, SYLVAIN |
分类号 |
G11C8/00;G11C5/14 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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