| 摘要 |
The present invention is provided with the following: a transmission port (313) and reception port (314) for communicating with another network unit; a system bus I/F unit (311) for communicating with a synchronization target; n (where n is an integer of 2 or greater) delay counters (316-1, 316-2) for counting a predetermined length of time; a delay counter control unit (317) for causing the delay counters (316-1, 316-2) to count a cycle that is n-fold a predetermined cycle upon receipt of a synchronous packet inputted in the predetermined cycle from the reception port (314), and for controlling the delay counters (316-1, 316-2) so that the counts in each of the delay counters (316-1, 316-2) are cleared at different times; and a synchronous pulse output unit for outputting a synchronous pulse to the synchronization target via the system bus I/F unit (311) if there is a delay counter (316-1, 316-2) for which the count value since clearing is a value equal to a synchronous pulse output value. |
