| 摘要 |
<p>The present invention relates to a single poly electrically erasable and programmable ROM (EEPROM) memory and more particularly, to a single poly EEPROM in which the number of used MOS elements is reduced and the size of a single poly EEPROM cell is reduced without quality degradation in an existing complementary metal-oxide-semiconductor (CMOS) process. The present invention includes a CG morse capacitor (MC1) and TG sense transistor (MN1) emitting electrons of floating gate (FG) in an FM tunneling manner as well as a select transistor (MN2) reducing off-leakage current in a beatline (BL) in over elimination. Also, the EEPROM memory comprises single poly EEPROM cells sharing a P type well area (PW) of MN1 and MN2 and sharing a deep N well area (DNW) of a cell array. The EEPROM uses an FN tunneling method to increase a recognizable distance of an RFID tag chip in a write mode. The size of EEPROM cell which is layout through a 0.18 micrometers process is between 7.6 micrometers x 3.67 micrometers (=27f.89 micrometers^2), which reduces the size of a bit cell by 32.4% compared to a conventional cell as well as reduces the number of used MOS elements.</p> |
