| 摘要 |
<p>A PoP package structure is disclosed, including at least two layers of carrier boards (109, 106, 103) that are packaged and stacked in sequence. Chips (108, 105, 102) are arranged on the top side of the carrier boards (109, 106, 103), and heat sinks (107, 104) are arranged on the bottom side of other carrier boards (106, 103) than the layer-1 carrier board (109), where a pad (110) welded to a system board is arranged on the bottom side of the layer-1 carrier board (109). Chips (108, 105) on other carrier boards (109, 106) than a top-layer carrier board (103) are surface-mounted onto heat sinks (107, 104) adjacent to the chips (108, 105). In the structure, a heat sink is arranged on the bottom side of a carrier board other than the layer-1 carrier board to dissipate heat for the chip (bare silicon or packaged chip) on the carrier board of the upper layer. The heat sink increases the heat dissipation area of the chip, enhances the heat dissipation capabilities of the PoP stacked packages massively, breaks the bottleneck of the high-density integration and miniaturization of the PoP stacked packages, and enhances the packaging density of the PoP stacked packages.</p> |
