发明名称 Method and system for model-based design and layout of an integrated circuit
摘要 A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
申请公布号 US8645887(B2) 申请公布日期 2014.02.04
申请号 US201213535242 申请日期 2012.06.27
申请人 LAI YA-CHIEH;GENNARI FRANK E.;MOSKEWICZ MATTHEW;DODDI SRINIVAS;LEI JUNJIANG;FANG WEIPING;LAY KUANGHAO;CADENCE DESIGN SYSTEMS, INC. 发明人 LAI YA-CHIEH;GENNARI FRANK E.;MOSKEWICZ MATTHEW;DODDI SRINIVAS;LEI JUNJIANG;FANG WEIPING;LAY KUANGHAO
分类号 G06F17/50 主分类号 G06F17/50
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